OS Memory Management

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Question 1

Which of the following page replacement algorithms suffers from Belady’s anomaly?
  • FIFO
  • LRU
  • Optimal Page Replacement
  • Both LRU and FIFO
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Question 2

What is the swap space in the disk used for?
  • Saving temporary html pages
  • Saving process data
  • Storing the super-block
  • Storing device drivers
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Question 3

Increasing the RAM of a computer typically improves performance because:
  • Virtual memory increases
  • Larger RAMs are faster
  • Fewer page faults occur
  • Fewer segmentation faults occur
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Question 4

A computer system supports 32-bit virtual addresses as well as 32-bit physical addresses. Since the virtual address space is of the same size as the physical address space, the operating system designers decide to get rid of the virtual memory entirely. Which one of the following is true?
  • Efficient implementation of multi-user support is no longer possible
  • The processor cache organization can be made more efficient now
  • Hardware support for memory management is no longer needed
  • CPU scheduling can be made more efficient now
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Question 5

A CPU generates 32-bit virtual addresses. The page size is 4 KB. The processor has a translation look-aside buffer (TLB) which can hold a total of 128 page table entries and is 4-way set associative. The minimum size of the TLB tag is:
  • 11 bits
  • 13 bits
  • 15 bits
  • 20 bits
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Question 6

Virtual memory is
  • Large secondary memory
  • Large main memory
  • Illusion of large main memory
  • None of the above
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Question 7

Page fault occurs when

  • When a requested page is in memory

  • When a requested page is not in memory

  • When a page is corrupted

  • When an exception is thrown

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Question 8

Thrashing occurs when
  • When a page fault occurs
  • Processes on system frequently access pages not memory
  • Processes on system are in running state
  • Processes on system are in waiting state
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Question 9

A computer uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization. The page table base register stores the base address of the first–level table (T1), which occupies exactly one page. Each entry of T1 stores the base address of a page of the second–level table (T2). Each entry of T2 stores the base address of a page of the third–level table (T3). Each entry of T3 stores a page table entry (PTE). The PTE is 32 bits in size. The processor used in the computer has a 1 MB 16 way set associative virtually indexed physically tagged cache. The cache block size is 64 bytes. What is the size of a page in KB in this computer?

  • 2

  • 4

  • 8

  • 16

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Question 10

Consider data given in the above question. What is the minimum number of page colours needed to guarantee that no two synonyms map to different sets in the processor cache of this computer? (GATE CS 2013)

  • 2
  • 4
  • 8
  • 16
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