VHDL is one of the type of hardware description language which describes the behavior of an integrated circuit or system which is used to implement physical circuit or system. VHDL is an abbreviation for VHSIC which stands for Very High Speed Integrated Circuit Hardware Description Language.
In this article, we will explore Very High Speed Integrated Circuit Hardware Description Language ( VHDL ). We will also see overview of Verilog language and its comparison with VHDL language. We will elaborate on its features, and its elements, modeling styles and objects. Furthermore, we will explore data types and operators in VHDL. Towards the end, we will review advantages and disadvantages of VHDL.
What Are Hardware Description Languages (HDLs)?
Hardware Description Languages(HDL) are special programming languages used to describe the structure and behavior of electronic circuits. Hardware Description Languages are required for designing various electronic components such as processors, motherboards and Field Programmable Gate Arrays. The difference between the traditional programming languages and the Hardware Description Languages is that Hardware Description Languages operate with respect to clock signals and delays. In Hardware Description Languages time is an important parameter.
What is VHDL ?
VHDL is one of the type of hardware description language which describes the behavior of an integrated circuit or system which is used to implement physical circuit or system. VHDL is an abbreviation for VHSIC which stands for Very High Speed Integrated Circuit Hardware Description Language. VHDL is a standard ,portable, reusable and vendor independent language. VHDL program code can be used to implement the circuit in programmable device like Complex Programmable Logic Device (CPLD) , Field Programmable Gate Array (FPGA) or used for fabrication of an ASIC chips. It is a hardware description language that can be used to model a digital system at many levels of abstraction.
What is Verilog ?
Verilog is a hardware description language (HDL) which is used to describe the structure and behavior of digital circuits. It is a text based language that is used by programmers to design and simulate circuits before building them physically. Verilog is a standard language verified by Institute of Electrical and Electronics Engineers (IEEE) . Similar to VHDL, Verilog also has concurrency feature which provides modeling concurrent processes in a hardware system. Verilog has multiple abstraction levels that means we can describe a circuit at different levels. This language is well suited for designing of complex digital circuits because it has ability to handle large scale projects effectively.
Comparison of VHDL and Verilog
VHDL | Verilog |
|---|
VHDL is based on Pascal or ADA language | Verilog is based on C programming language |
VHDL is not case sensitive. | Verilog is case sensitive. |
VHDL does not have compiler directives | Verilog has compiler directives |
VHDL does not supports transistor level modelling | Verilog supports transistor level modelling. |
VHDL support user defined data types. | Verilog does not support user defined data types. |
Features of VHDL
1. It supports hierarchy. It uses set of components and interconnects them, each component can also be modeled as a set interconnected sub components.
2. It supports both synchronous and asynchronous timing models.
3. It supports various digital modeling techniques like Finite State Machine (FSM), Algorithmic description and Boolean expressions.
4.It is not case sensitive.
5. The logical operation and timing behavior of a design can be stimulated.
6. It is not technology specific i.e. it can work with Xilinx, Lattice, Atmel series of CPLDs or FPGAs.
Elements of VHDL
Entity - Entity is the description of inputs and outputs of the design. An entity is the most basic building block in the design. A design can have more than one entity blocks. An entity statement declares the design name. Then it defines input output parameters and ports of the design entity. For each port, its mode and type are defined. It is equivalent to pin configuration of an IC. An entity describes input and output signal names. Each port in the port list must be given a name, data flow direction and a type. VHDL design description must include only one entity.
The Syntax of an Entity is :
entity ENTITY_NAME is
port (port list) ;
end ENTITY_NAME
Architecture - All entities that are declared have an architecture associated with it. Architecture describes the behavior of the entity. An entity can have multiple architectures. Architecture assigned to an entity describes internal relationship between input and output of the entity. First part of the architecture may contain declarations of types, signal, constants, subprograms etc.
The Syntax of Architecture is :
architecture ARCHITECTURE_NAME OF ENTITY_NAME is
begin
statements (relation between input and output);
end ARCHITECTURE NAME;
Configuration - A configuration statement is used for binding a component instance to an entity architecture pair, when there are multiple architectures for a single entity. It is used during design instantiation (putting together the pieces) to map component instances to specific entity-architecture pairs.
Package - A package used to build the design using data types and sub programs which are commonly used. Packages are used for increasing code reusability, organization, and better management of design elements.
Library - Library is used to store entities, architectures and packages used in VHDL program .
VHDL Modeling Styles
The different modeling types provided by VHDL are :
Data Flow modeling: A data flow model specifies, how data is been processed through the circuit using concurrent signal assignment statements and block statements. There is no specified ordering of these statements therefore the ordering of these statements in an architecture body is not important. It requires Boolean equations for designing circuit specifications. Boolean equations are series of equations defining signal relationship. Data flow modeling focuses mainly on the how data flows through the system instead of focusing on components. Data flow Modeling is suitable for simple logic which allows us to express data flow efficiently. However it can be complicated for intricate designs with complex control flow.
Behavioral modeling: Behavioral modeling follows a more procedural approach, similar to writing a program. In Behavioral modeling processes with control flow statements like if-then-else define how the design should react to input and update its output. The set of instructions written by the programmer decide the system's behavior under different conditions. Behavioral modeling has great flexibility for modeling complex logic with control flow. Hence it is suitable for describing intricate algorithms within the hardware. Behavioral modeling is great for describing how things work, but it is difficult to see exactly how the hardware is built compared to structural modeling.
Structural Modeling: In Structural modeling the user don't need to design the internal working of each component. We can simply use them in the design by giving them unique names. Hence it provides a clear, circuit-like view where each block is a known as entity. Since structural modeling uses pre-verified components, troubleshooting becomes easier. Focusing on connections is more important rather than internal behavior.
Data Types in VHDL
1. Scaler Data Types
(a) Integer types
(b) Real types
(c) Enumerated types
(d) Physical types
2. Composite Data Types
(a) Array types
(b) Record types
Integer type
The Integer data types are mathematical integers. An integer type has set of values which fall within a specified integer range.
Real type
The real data type are used in calculations with decimals where representing and manipulating values with fractional parts is done. It is useful for noting down the things like voltage levels (e.g. 3.14 volts) or calculations involving continuous quantities. Expressing very large or small numbers in a compact way becomes possible due to real data type.
Enumerated type
An enumerated data type in VHDL defines a custom set of named constants, similar to creating a list of choices. It is user defined means the user/programmer can create the list of valid values e.g. 'high' , 'low' for logic states .
Physical type
The physical data type in VHDL is used to describe physical quantities in the hardware model. It bridges the gap between design and the real world. It represents real- world units or things like time (seconds), length (meters), or voltage (volts) directly in the code.
Array type
An array data type in VHDL consists of elements that have same data type. The elements in an array are arranged in a specific order. Elements in an array are accessed using an index. All elements within the array must be of the same data type e.g., all integers, all Booleans.
Record type
A record data type contains elements of different data types. Unlike arrays, record data type can hold elements of different data types e.g. integer for temperature, Boolean for on/off state, string for sensor name ). Each element within the record has a unique name (like labels on the form), which makes it clear what kind of data it holds (e.g., "temperature" : integer , "sensor_on" : boolean, "sensor_id" : string).
VHDL Objects
The VHDL objects are used to represent and store data in the system. It holds the values of a specified type. VHDL objects serves a specific purpose within the hardware design. All VHDL objects must have a specific data type associated with them, defining the kind of information they can hold (e.g., integer, boolean, bit vector).
- Signal: Signals holds a list of values which include the current value of the signal and a set of possible future values that are to be appear on the signal. It represents wire within a circuit. The scope of the signal is within the whole architecture. Signals connect entities, which helps in exchanging data.
- Variables: Variables can store values that change during the simulation. Variables are typically declared within processes and used to hold temporary data or control flow information. Variables can be used within processes to manipulate data and control the flow of execution. The scope of the variable is within a process.
- Constants: Constants are fixed, unchanging values assigned a name. These are fixed labels assigned to specific values. Once constant's value is assigned, it cannot be changed. Constants declared in a package are accessible throughout the design. Constants are used within a single entity or process to store and manipulate data.
VHDL Operators
The operators in the VHDL language are classified into the following categories:
1. Logical Operators
- AND ( & ) : AND operator performs a logical AND operation. This operator returns true if both the operands are true, if not it returns false.
- OR ( | ) : OR operator performs a logical OR operation. This operator returns true if at least one of the operand is true, if not it returns false.
- NOT (~) : NOT operator performs a logical negation. It flips the value of a single operand.
- XNOR (XNOR) : XNOR operator performs an exclusive NOR operation. The output is True or 1 only when both operands are the same either both True or both False.
- NAND (Not AND) : NAND operator Performs a logical AND operation and then inverts the result. Here the output is False or 0 only when both operands are True. In all other cases the output is True or 1.
- NOR (Not OR) : NOR operator Performs a logical OR operation and then inverts the result. Here the output is True or 1 only when both operands are False.
2. Shift Operators
The shift operators are as follows :
sll | shift left logical |
srl | shift right logical |
sla | shift left arithmetic |
sra | shift right arithmetic |
rol | rotate left logical |
ror | rotate right logical |
3. Arithmetic Operators
The arithmetic operators are as follows :
Addition (+) | Adds two operands. ( a+b ) |
Subtraction (-) | Subtracts the second operand from the first. ( a-b ) |
Multiplication (*) | Multiplies two operands. ( a*b ) |
Division (/) | Divides the first operand by the second. ( a/b ) |
Modulo (%) | Calculates the remainder after division. ( a%b ) |
Exponentiation (**) | Raises the first operand to the power of the second. ( a**b ) |
Advantages of VHDL
- VHDL is a standard language and has simpler syntax like Ada language.
- It describes the behavior of digital circuits and systems using testbench.
- It is a strongly typed language. It supports a multi-level abstraction.
- Signed and unsigned numbers can be used in VHDL.
- VHDL language supports readily available tools, supports all CAD tools.
Disadvantages of VHDL
- It has more wordy and complicated coding.
- Every bit vector use the keyword "down to" is very tedious.
- Sometimes very long sensitivity list must have in each process.
- Missing a single signal in sensitivity list may fail simulation and synthesis.
- Synthesized hardware from a VHDL description may not always be immediately obvious.
Conclusion
In summary, VHDL is one of the type of hardware description language which describes the behavior of an integrated circuit or system which is used to implement physical circuit or system. In this article we have seen what are Hardware Description Languages (HDLs), what is VHDL, what is Verilog, comparison between VHDL and Verilog , different features of VHDL, what are elements of VHDL, modeling styles in VHDL , VHDL data types, objects, operators, advantages and disadvantages of VHDL.
1. How is VHDL different from Verilog ?
While both are HDLs, VHDL excels in dataflow description, where as Verilog offers a wider range of constructs for procedural modeling.
2. Can I use VHDL to program microcontrollers ?
No, VHDL is primarily for designing digital circuits like FPGAs, not for programming microcontrollers which typically use C-based languages.
3. What are the benefits of using VHDL ?
VHDL allows simulation for testing circuits before building them and offers portability across design tools.
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